The present invention relates to an amplifying type solid-state imaging device and a method of manufacturing the same.
Recently, in accordance with an increasing demand that a solid-state imaging device provides a higher resolution, there has been developed an amplifying type solid-state imaging device in which charges of light signal are amplified at every pixel. This amplifying type solid-state imaging device includes an MOS (metal-oxide-semiconductor) transistor disposed at every pixel for carrying out a certain signal-conversion in which photoelectric-converted charge is accumulated in the pixel and this charge is outputted as a current-modulated component of a transistor.
FIGS. 1 and 2 of the accompanying drawings show an amplifying type solid-state imaging device.
As shown in FIG. 2, an amplifying type solid-state imaging device 1 comprises a first conductivity-type, e.g., p-type silicon semiconductor substrate 2 on which a second conductivity-type, i.e., n-type semiconductor region, i.e., overflow-barrier region 3 and a p-type semiconductor well region 4 are formed. Annular gate electrodes 6 capable of transmitting light are formed on the p-type semiconductor well region 5 through a gate-insulating film 5 made of SiO.sub.2 or the like. On the p-type semiconductor well regions 4 corresponding to a central aperture and outer peripheries of the annular gate electrodes 6 are formed an n-type source region 7 and n-type drain regions 8 by self-alignment using the gate electrode 6 as a mask, thereby resulting in an MOS transistor (hereinafter referred to as "pixel MOS transistor") 9 serving as one pixel being arranged. The annular gate electrode 6 may be made of a thin or transparent material which can be prevented from absorbing light as much as possible. In this embodiment, the annular gate electrode 6 may be made of a thin film polycrystalline silicon. In FIG. 2, reference numeral 10 depicts an interlevel insulator.
As shown in FIG. 1, a plurality of pixel MOS transistors 9 are disposed in a matrix fashion. The source regions of the pixel MOS transistors 9 corresponding to respective columns are connected to common signal lines 11 of first aluminum (Al) layer, for example, formed along the vertical direction. Vertical scanning lines 12 made of second Al layers, for example, are formed at the positions corresponding to respective rows of the pixel MOS transistors 9 so as to become perpendicular to the signal lines 11 in the horizontal direction.
An interconnection layer made of polycrystalline silicon, i.e, U-shaped contact buffer layer 13 is formed across the annular gate electrodes 6 of two pixel MOS transistors 9 adjacent in the horizontal direction and which is extended to the corresponding vertical scanning line 12. Both ends of the contact buffer layer 13 are electrically connected to the two pixel MOS transistors, i.e., the gate electrodes 6, 6 and the intermediate portion of the contact buffer layer 13 is connected to the vertical scanning line 12.
In FIG. 1, reference numeral 15 denotes a contact portion provided between the contact buffer layer 13 and the vertical scanning line 12, and reference numeral 16 denotes a contact portion provided between the source region 7 and the signal line 11.
A drain power-supply line 18 made of a first Al layer, for example, connected to the drain region 8 is formed between the pixel MOS transistors 9 which are not provided across the contact buffer layer 13. In FIG. 1, reference numeral 17 denotes a contact portion between the drain region 8 and the drain power-supply line 18.
In the pixel MOS transistor 9, as shown in FIG. 2, light passed through the annular gate electrode 6 produces electrons-holes, and holes h are accumulated in the p-type semiconductor well region 4 formed under the annular gate electrode 6 as signal charges. When the pixel MOS transistor 9 is turned on on application of high voltage to the annular gate electrode 6 through the vertical scanning line 12, a drain current I.sub.d is flowed to the surface channel and this drain current I.sub.d is changed by the signal charge h so that this drain current I.sub.d is outputted through the signal line 11 and the changed amount is developed as the signal output.
In the above-mentioned amplifying type solid-state imaging device 1, only the n-type source region 7 and the n-type drain region 8 are formed on the p-type semiconductor well region 4 as shown in FIGS. 3 and 4 which are a fragmentary plan view and a fragmentary cross-sectional view of the pixel MOS transistor 9.
As shown in a potential diagram of FIG. 5 which illustrates a simulated result of potential obtained in the charge accumulated state of the pixel MOS transistor, a potential barrier at the drain portion serving as a channel-stopper region is not formed at all except the surface of the drain region. Moreover, a potential barrier of the overflow-barrier region 3 is at about a diffusion potential and is not formed substantially.
As a result, a blooming in which accumulated signal charges are leaked to adjacent pixel MOS transistor side tends to occur, and hence an amount of signal charges accumulated in the pixels is not sufficient for the amplifying type solid-state imaging device.